1. Field of the Invention
This invention generally relates to analog-to digital and digital-to-analog data conversion and, more particularly, to a system and method for customizing a universal data conversion device, capable of potentially performing many different types of functions.
2. Description of the Related Art
As noted in Wikipedia, an ADC is a device that converts a continuous physical quantity, such as voltage, to a digital number that represents the analog quantity's amplitude. The conversion involves quantization of the input, so it necessarily introduces a small amount of error. Instead of doing a single conversion, an ADC often performs the conversions by sampling the input periodically. The result is a sequence of digital values that have converted a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal.
An ADC is often characterized by its input bandwidth, the range of input signal frequencies it can measure, and its signal-to-noise ratio (SNR). SNR is the accuracy with which a signal can be measured with respect to the noise it introduces. The SNR of an ADC is influenced by many factors, including the resolution, which is the number of output levels to which it can quantize a signal. Linearity and accuracy, or how well the quantization levels match the true analog signal, and aperture jitter, small timing errors that introduce additional errors, also influence the SNR. The SNR of an ADC is often summarized in terms of its effective number of bits (ENOB), the number of bits of each measure it returns that are on average not noise. ADCs are chosen to match the bandwidth and required SNR of the signal to be quantized.
Conventionally, if an ADC operates at a sampling rate greater than twice the bandwidth of the signal, then perfect reconstruction is possible given an ideal ADC and neglecting quantization error. The presence of quantization error limits the SNR of even an ideal ADC. However, if the SNR of the ADC exceeds that of the input signal, its effects may be neglected resulting in an essentially perfect digital representation of the input signal.
The resolution of the converter indicates the number of discrete values it can produce over the range of analog values. The resolution determines the magnitude of the quantization error and therefore determines the maximum possible average SNR for an ideal ADC without the use of oversampling. The values are usually stored electronically in binary form, so the resolution is usually expressed in bits. In consequence, the number of discrete values available, or “levels”, is assumed to be a power of two. For example, an ADC with a resolution of 8 bits can encode an analog input to one in 256 different analog levels, since 28=256. Resolution can also be defined electrically, and expressed in volts. The minimum change in voltage required to guarantee a change in the output code level digital signal is called the least significant bit (LSB) voltage.
The analog signal is continuous in time and it is necessary to convert this to a flow of digital values. Therefore, a rate must be determined at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate or sampling frequency of the converter. A continuously varying bandlimited signal can be sampled as the signal values at intervals of time T, the sampling time, are measured and stored. Then, the original signal can be exactly reproduced from the discrete-time values by an interpolation formula. The accuracy is limited by quantization error. However, this faithful reproduction is typically only possible if the sampling rate is higher than twice the highest frequency of the signal. This is essentially what is embodied in the Shannon-Nyquist sampling theorem.
An ADC works by sampling the value of the input at discrete intervals in time. Provided that the input is sampled above the Nyquist rate, defined as twice the highest frequency of interest, then all frequencies in the signal can be reconstructed. If frequencies above half the Nyquist rate are sampled, they are incorrectly detected as lower frequencies, a process referred to as aliasing. Aliasing occurs because instantaneously sampling a function at two or fewer times per cycle results in missed cycles, incorrectly giving the appearance of a lower frequency. To avoid aliasing, the input to an ADC may be low-pass filtered to remove frequencies above half the sampling rate. This filter is called an anti-aliasing filter.
Although aliasing in most systems is unwanted, in some aspects it may be exploited to provide simultaneous down-mixing of a band-limited high frequency signal. The alias is effectively the lower heterodyne of the signal frequency and sampling frequency.
Signals are often sampled at the minimum rate required, for economy, with the result that the quantization noise introduced is white noise spread over the whole pass band of the converter. If a signal is sampled at a rate much higher than the Nyquist frequency, and then digitally filtered to limit it to the signal bandwidth, there are many advantages. A digital filter can have better properties, such as a sharper rolloff, than an analog filter, so a sharper anti-aliasing filter can be realized. Subsequent to filtering, the signal can be downsampled. This technique creates an effectively larger resolution than can be provided by an ADC device acting alone.
These are many ways of implementing an electronic ADC. A direct-conversion ADC or flash ADC has a bank of comparators sampling the input signal in parallel, each firing for their decoded voltage range. The comparator bank feeds a logic circuit that generates a code for each voltage range. Direct conversion is very fast, capable of gigahertz sampling rates, but usually has only 8 bits of resolution or fewer, since the number of comparators needed, 2N−1, doubles with each additional bit, requiring a large, expensive circuit. ADCs of this type typically have a large die size, a high input capacitance, high power dissipation, and are prone to produce glitches at the output (by outputting an out-of-sequence code). U.S. Pat. No. 8,519,876, invented by Zhi-Ming Lin, filed on Mar. 27, 2012, is incorporated herein by reference, and provides an example of a flash ADC.
A successive-approximation ADC uses a comparator to successively narrow a range that contains the input voltage. At each successive step, the converter compares the input voltage to the output of an internal digital to analog converter which might represent the midpoint of a selected voltage range. At each step in this process, the approximation is stored in a successive approximation register (SAR). U.S. Pat. No. 8,542,144, invented by A. Coban, filed on Sep. 30, 2011, is incorporated herein by reference, and provides an example of a successive-approximation ADC.
A ramp-compare ADC produces a saw-tooth signal that ramps up or down then quickly returns to zero. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, and the timer's value is recorded. Timed ramp converters require the least number of transistors. The ramp time is sensitive to temperature because it is dependent upon the circuit generating the ramp.
The Wilkinson ADC is based on the comparison of an input voltage with that produced by a charging capacitor. The capacitor is allowed to charge until its voltage is equal to the amplitude of the input pulse. A comparator determines when this condition has been reached. Then, the capacitor is allowed to discharge linearly, which produces a ramp voltage. At the point when the capacitor begins to discharge, a gate pulse is initiated. The gate pulse remains on until the capacitor is completely discharged. Thus, the duration of the gate pulse is directly proportional to the amplitude of the input pulse. This gate pulse operates a linear gate which receives pulses from a high-frequency oscillator clock. While the gate is open, a discrete number of clock pulses pass through the linear gate and are counted by the address register. The time the linear gate is open is proportional to the amplitude of the input pulse, thus the number of clock pulses recorded in the address register is proportional to the amplitude. Alternatively, the charging of the capacitor can be monitored, rather than the discharge.
An integrating ADC, also known as a dual-slope or multi-slope ADC, applies an unknown input voltage to the input of an integrator and allows the voltage to ramp for a fixed time period (the run-up period). Then a known reference voltage of opposite polarity is applied to the integrator, and is allowed to ramp until the integrator output returns to zero (the run-down period). The input voltage is computed as a function of the reference voltage, the constant run-up time period, and the measured run-down time period. The run-down time measurement is usually made in units of the converter's clock, so longer integration times allow for higher resolutions. The speed of the converter can be improved by sacrificing resolution.
A delta-encoded (tracking) ADC or counter-ramp has an up-down counter that feeds a digital-to-analog converter (DAC). The input signal and the DAC both go to a comparator. The comparator controls the counter. The circuit uses negative feedback from the comparator to adjust the counter until the DAC's output is close enough to the input signal. The number is read from the counter. Delta converters have very wide ranges and high resolution, but the conversion time is dependent on the input signal level. Some converters combine the delta and successive approximation approaches; this works especially well when high frequencies are small in magnitude. U.S. Pat. No. 8,358,231, invented by Killat et al., with a priority date of Feb. 21, 2011, which is incorporated herein by reference, provides an example of a delta-encoded ADC.
As noted in U.S. Pat. No. 8,368,571, invented by Eric Siragusa, filed on Mar. 31, 2011, and incorporated herein by reference, a pipelined ADC 20 converts the overall analog input AIN delivered to the first stage 24 by successively approximating in turn the analog input AI at each stage 24, to the predetermined bit width of that stage 24, then generating and amplifying the analog residue AR representing the unconverted remainder of the analog input AI at that stage 24, and passing the amplified residue MR to the next stage 24 and repeating the process. Ultimately, the ADC 20 can convert the original analog input AIN by combining the digital output DO produced by each of the individual stages 24, which can be performed by a delay and combine circuit 44, to successively build corresponding digitized residues DR into the overall digital output DOUT. Other architectures are known in the art that can be configured to improve resolution.
An oversampling ADC, oversamples an analog input signal by a large factor and filters the desired signal band. In a sigma-delta version of this ADC, the resulting signal, along with the error generated by the discrete levels of a flash ADC, is fed back and subtracted from the input to the aliasing filter. This negative feedback has the effect of noise shaping the error due to the flash, so that it does not appear in the desired signal frequencies. A digital filter (decimation filter) follows the ADC that reduces the sampling rate, filters off unwanted noise, and increases the resolution of the output. The use of “noise-shaping” through analog feedback mechanisms is not required to benefit from oversampling, but noise shaping makes oversampling more efficient (more resolution with less oversampling). However, this process requires approximately greater than 16× oversampling to be effective, as well as analog filter and feedback mechanisms. Simple decimation filtering of a flat (white) noise data converter yields an effective 3 dB SNR for every octave of oversampling. US 2010/0283649, invented by Bos et al., with a priority date of May 7, 2010, is incorporated herein by reference, and provides an example of a sigma-delta ADC.
A time-interleaved ADC uses M parallel ADCs where each ADC samples data every M:th cycle of the effective sample clock. The result is that the sample rate is increased M times compared to what each individual ADC can manage. Technologies exist to correct time-interleaving mismatch errors. An ADC with an intermediate frequency modulation (FM) stage first uses a voltage-to-frequency converter to convert the desired signal into an oscillating signal with a frequency proportional to the voltage of the desired signal, and then uses a frequency counter to convert that frequency into a digital count proportional to the desired signal voltage. U.S. Pat. No. 8,542,142, invented by Stein et al., filed on Feb. 21, 2013, is incorporated herein by reference, and provides an example of an interleaved ADC.
A time-stretch analog-to-digital converter (TS-ADC) digitizes a very wide bandwidth analog signal, which cannot be digitized by a conventional electronic ADC, by time-stretching the signal prior to digitization. This technique effectively slows the signal down in time and compresses its bandwidth. As a result, an electronic backend ADC that would have been too slow to capture the original signal, can now capture this slowed down signal.
Other types of ADCs, and variations of the above-mentioned ADC type include the following. U.S. Pat. No. 8,542,140, invented by Chen et al., filed on Jan. 12, 2012, is incorporated herein by reference, and provides an example of an exponential-logarithmic ADC. U.S. Pat. No. 8,471,751, invented by Zhenning Wang, filed on Jun. 30, 2011, is incorporated herein by reference, and provides an example of a time-to-digital converter (TDC).
A digital-to-analog converter (DAC) converts a digital signal, typically represented by a series of binary logic symbols, into an analog current or voltage. In a pulse-width modulator DAC type, a current or voltage is switched into a low-pass analog filter with a duration determined by the digital input code. Oversampling or interpolating DACs, such as the delta-sigma DAC, use a pulse density conversion technique. The DAC is driven with a pulse-density modulated signal, created with the use of a low-pass filter, step nonlinearity (the actual 1-bit DAC), and negative feedback loop, in a technique called delta-sigma modulation. This results in an effective high-pass filter acting on the quantization (signal processing) noise, thus steering this noise out of the low frequencies of interest into the megahertz frequencies of little interest, which is called noise shaping.
The binary-weighted DAC contains individual electrical components for each bit of the DAC connected to a summing point. These precise voltages or currents sum to the correct output value. A switched resistor DAC contains of a parallel resistor network. Individual resistors are enabled or bypassed in the network based on the digital input. A switched current source or current steering DAC uses different current sources selected by the digital input. A switched capacitor DAC contains a parallel capacitor network. Individual capacitors are connected or disconnected with switches based on the input.
A R-2R ladder DAC is a binary-weighted DAC that uses a repeating cascaded structure of resistor values R and 2R. A successive-approximation or cyclic DAC successively constructs the output during each cycle. Individual bits of the digital input are processed each cycle until the entire input is accounted for.
The thermometer-coded DAC contains an equal resistor or current-source segment for each possible value of DAC output. An 8-bit thermometer DAC would have 255 segments, and a 16-bit thermometer DAC would have 65,535 segments. To minimize the number of components, the DAC may use banks of segments, where a digital value is represented by a combination segment values. This segmented DAC combines the thermometer-coded principle for the most significant bits and the binary-weighted principle for the least significant bits. In this way, a compromise is obtained between precision (by the use of the thermometer-coded principle) and number of resistors or current sources (by the use of the binary-weighted principle).
Conventionally, in designing a product, the manufacturer of an electrical system determines the performance required by an ADC or DAC, specifying characteristics such the data rate, dynamic range, digital output signal resolution, and SNR. Upon determining the circuit performance required, the circuit is designed from discrete components, or an integrated circuit (IC) is purchased from a vendor. In the case of the IC, the printed circuit board (PCB) upon which the circuit is mounted must be designed to conform to a pre-existing IC pin out, or a custom IC designed with a pin out that conforms to the PCB.
An advancement in the manufacturing process is described in U.S. Pat. No. 8,548,071, where the IC design process begins by selecting a predetermined number of ADCs (or DACs), and assigning the ADCs to input/output ports based upon the desired data rate. Configuration data is generated for programmable interconnects between the ports and ADCs, which is then loaded into the IC (FIGS. 3, 18, and 19). Advantageously, data rate, power, and resolution design requirements can be addressed by selecting the number of parallel channels or by the use of an interleaving technique (FIGS. 4-8). In some aspect, the routing to different ADC circuits can be made to periodically change based upon clock speed (FIG. 11). While this process may simplify the design of an IC, the problem remains that once the IC is designed, its use is still limited to a particular customer and a particular implementation. This problem necessarily impacts overall product performance and options, as well as ADC component lead times and costs.
It would be advantageous if it were possible to design a data converter IC, fabricated initially to potentially perform a wide variety of data converter functions, which could be simply modified during fabrication or in the field to perform the particular function desired by the user.